Enhancing 3D NAND performance and reliability through overlay control

Abstract

As microelectronic devices undergo continuous evolution, the ongoing miniaturization of semiconductor chips, coupled with an escalating number of layers, presents a huge challenge in meeting the progressively stringent overlay requirements for every successive generation of chips. Overlay, a metric quantifying the positional deviation between adjacent layers within the semiconductor die, constitutes one of the three critical parameters essential for evaluating the performance of photolithography scanners. It plays a pivotal role in influencing the electrical properties, lifespan, and reliability of integrated circuits (IC).

In Micron's latest 3D NAND memory chip, there exists an overlay error between its Complementary Metal-Oxide-Semiconductor (CMOS) contact and the Wordline (WL) contact. While there has been extensive research into resolving general overlay errors, there is little to no research that can be used effectively on the specific overlay issue in Micron's latest 3D NAND memory chip. Hence, a research gap exists in characterizing and identifying the causes of overlay issues in this specific context.

In this study, process flow studies, evaluation of wafer-level process changes, wafer reticle design studies, and stress studies have been conducted to comprehensively characterize, identify, and resolve the root causes of wafer-level and die-level overlay issues. We achieved a 1.3% yield gain on the wafer-level issue and managed to further characterize the unique die-level overlay issue with a possible new lead to resolve this issue.