Low power logic-in-memory circuit design

Abstract

This paper presents an analysis of power dissipation between conventional 6T SRAM memory arrays and SRAM memory arrays employing power reduction techniques. This study aims to assess the power efficiency of these power reduction techniques, which is crucial for low power applications in modern electronic devices. The 6T SRAM memory array made up of conventional 6T SRAM memory cells would be used as a baseline for comparison against other power optimized memory arrays. In conjunction with the power efficiency, varying supply voltage and temperature will be utilized to provide a more comprehensive set of data. The results show that these power reduction techniques is effective in better optimizing power. The research will involve tools such as Cadence Virtuoso and TSMC 65nm CMOS process technology.