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https://hdl.handle.net/10356/176988
Title: | Design of a low dropout voltage regulator (LDO) with an embedded current-mode voltage reference without the use of BJT | Authors: | Jiang, Xuewei | Keywords: | Engineering | Issue Date: | 2024 | Publisher: | Nanyang Technological University | Source: | Jiang, X. (2024). Design of a low dropout voltage regulator (LDO) with an embedded current-mode voltage reference without the use of BJT. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/176988 | Project: | A2205-231 | Abstract: | This report proposes a MOSFET-only design of the Low-power, Low-voltage, Low Dropout (LDO) Voltage regular with an embedded voltage reference in current-mode operation. The LDO can generate 0.7V regulated voltage over a wide supply voltage range from 0.9 V to 1.5 V with a line regulation of 6.4 mV / V and load regulation of 8.22 uV / A. In the full load condition, the LDO is capable of providing 20mA with 0.9V input voltage. With NMOS in subthreshold, the design allows the LDO circuit to operate with low current and power consumption to perform a 14.4 ppm/°C temperature coefficient under full load conditions in the range from -30°C to 110°C. The design process is done using the virtuoso tool in the Linux system with Global Foundries 55nm BCD-lite technology. | URI: | https://hdl.handle.net/10356/176988 | Schools: | School of Electrical and Electronic Engineering | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
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File | Description | Size | Format | |
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FYP Report_Jiang Xuewei.pdf Restricted Access | 4.13 MB | Adobe PDF | View/Open |
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