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|Title:||Smart ADC for bio-sensor interface||Authors:||Chen, Liang.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Control and instrumentation::Medical electronics||Issue Date:||2009||Abstract:||The emerging low-power portable biomedical sensory systems have pushed integrated circuits towards very low power design for sensor signal processing. Most often, it needs a low-power Analog-to-Digital (ADC) to handle signal processing effectively between the analog sensor signals and digital interface. As a result, the design of an ADC with built-in smart features for dedicated sensor applications will be able to improve the efficiency of the bio-sensing system. The project involves feasibility study, design, simulations and layout. Cadence behavior-level and transistor-level simulation tools will be used for circuit and system verification. The chip will be fabricated by commercial Multi-Project Wafer (MPW) service. The purpose of the report is to present the whole design flow of modern digital IC design, by the example of this Smart ADC design. It includes both the frontend design such as design specification, RTL coding, testbench writing as well as the design testing and verification, and the backend design such as logic synthesis and layout place and route. The design is also verified in the area of functionality and synthesizability. Meanwhile, Cadence Encounter Solution and Chartered Semiconductor 180nm IC Process 1.8-Volt SAGE-XTM v1.0 Standard Cell Library (CSM018) are used as EDA tools and standard cell library to realize the whole project, the tutorial of the Cadence Encounter Solution is provided as well. In this project, an ASIC pertaining to Smart ADC is achieved. An innovative method is introduced to construct an ADC with high accuracy (11-bit), low power consumption (750μW) and wide range of measurement (50Hz – 200kHz), Besides that, features of asynchronous data transmission and parallel-to-series converter are also constructed to provide a system-level solution. As the result of analysis this Smart ADC design in the field of chip area, power dissipation and timing response, this overall design is able to achieve the average power dissipation of 750μW under the worst case scenario and chip core area of 0.06 mm2.||URI:||http://hdl.handle.net/10356/17768||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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