Please use this identifier to cite or link to this item:
Title: Implementation of fast algorithms of discrete fourier transform with FPGA
Authors: Zhang, Yanghao.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing
Issue Date: 2009
Abstract: Fast Fourier transform (FFT) plays an important part as a signal processing function in many applications. This report will represent a single-path pipelined hardware structure and its implementation on field programmable gates-array (FPGA) for discrete Fourier transform (DFT) computation based on the radix-22 FFT algorithm. The proposed structure requires log4N-1 complex multipliers, log2N complex adder/subtractors and 2(N-1) complex data stores. Compared with the previous radix-22 SDF structure, the number of adder/subtractors is reduced by 50%. Compared with the previous radix-22 MDC structure, the number of both complex multipliers and adder/subtractors is reduced by 50%. The report will give the detailed description of the implementation of the structure on FPGA. At the same time, the in depth comparison between the proposed structure and radix-22 SDF structures will be presented.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
  Restricted Access
2.42 MBMicrosoft WordView/Open

Page view(s)

Updated on Nov 25, 2020


Updated on Nov 25, 2020

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.