Please use this identifier to cite or link to this item:
Title: Channel modeling and FPGA implementation for magnetic recording
Authors: Tan, Jing Jie.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2009
Abstract: This report aims to design and implement a channel model on the Xllinx Spartan-3E XC3S500E Field Programmable Gate Array (FPGA) board. The channel model basically comprises of two main parts, a Finite Impulse Response (FIR) filter and an irregular Low- Density Parity-Check (LDPC) encoder.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
  Restricted Access
Final Report1.84 MBAdobe PDFView/Open

Page view(s) 10

Updated on Feb 27, 2021


Updated on Feb 27, 2021

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.