Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/17851| Title: | Channel modeling and FPGA implementation for magnetic recording | Authors: | Tan, Jing Jie. | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits | Issue Date: | 2009 | Abstract: | This report aims to design and implement a channel model on the Xllinx Spartan-3E XC3S500E Field Programmable Gate Array (FPGA) board. The channel model basically comprises of two main parts, a Finite Impulse Response (FIR) filter and an irregular Low- Density Parity-Check (LDPC) encoder. | URI: | http://hdl.handle.net/10356/17851 | Schools: | School of Electrical and Electronic Engineering | Research Centres: | Centre for Integrated Circuits and Systems | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
| Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| eA2036081.pdf Restricted Access | Final Report | 1.84 MB | Adobe PDF | View/Open |
Page view(s) 50
472
Updated on Mar 27, 2025
Download(s)
9
Updated on Mar 27, 2025
Google ScholarTM
Check
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.