Design of hierarchy extractor for very large scale integration (VLSI) integrated circuit design

Abstract

Nowadays, electronic manufacturing technology has been developed tremendously and it allows the creation of monolithic integrated circuits that involve millions of transistors. Therefore, in view of the increasing complexity of VLSI Circuits, there is a need for sophisticated computer-aided design (CAD) tools to automate the synthesis and verification steps in the design of VLSI systems.

One of the highly demanded CAD tools is the hierarchy extractor, for the reason that automatic recognition of a high level structure from the different abstraction level netlist of a circuit design is important for many tasks in VLSI design.

In this FYP-URECA project, a design methodology for extracting the behavior of a Finite State Machine (FSM) from a RTL-level netlist is developed. Finite state machines are essential building block in the synthesis of large scale digital circuits for the reason that state machines can be use to model digital circuits which merge combinational logic and a memory element.

Several design steps have been proposed in this report which include the preparation phase of preparing the netlist file, the structural extraction phase with the purpose of separating the combinational and sequential logic into different clusters, and the behavioral recognition phase where the Binary Decision Diagram is used to model the sequential logic and generate the next state and output table.

This hierarchy extractor is then realized using Octave and Perl programming language. Functional verification of the whole program by using different circuits as test cases has also been performed.