Design, fabrication and characterization of a tunnel FET

Abstract

This report details and demonstrates a vertical silicon nanowire (SiNW) based tunneling field-effect transistor (TFET) using CMOS compatible technology. With Si P+-i-n+ tunneling junction, the TFET with a gate length of ~200 nm exhibits good subthreshold swing of ~70 mV/dec, superior DIBL of ~17 mV/V, and excellent Ion/Ioff ratio of 7 orders with a low Ioff (~7pA/um). The vertical SiNW based TFET is proposed to be an excellent candidate for ultra-low power and high density applications.