Please use this identifier to cite or link to this item:
Title: Design of high-speed dynamic element matching DAC for multi-bit delta-sigma modulators
Authors: Wang, Gaopeng
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
DRNTU::Engineering::Electrical and electronic engineering::Applications of electronics
Issue Date: 2009
Abstract: This project examines various dynamic-element-matching algorithms to improve the performance of delta-sigma modulator’s multi-bit DAC due to non-idealities in circuit. Simulations at system level are performed to verify and compare the performance of those algorithms. Then one of the algorithms, data-weighted-averaging algorithm is discussed in detail and implemented at transistor-level in Cadence with the CSM018IC process. A new implementation approach for the DWA algorithm is developed and tested at circuit level. From the simulation, it is verified the designed DAC with DWA algorithm is workable at sampling frequency of 500MHz with satisfying improvement in performance compared to without DWA algorithm.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
  Restricted Access
The cover page of the Report52.7 kBAdobe PDFView/Open
  Restricted Access
the mainbody of the report1.56 MBAdobe PDFView/Open

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.