Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/17983
Title: Effects of vacancies on device performance
Authors: Yan, Alan Yik Loon
Keywords: DRNTU::Engineering
Issue Date: 2009
Abstract: A process to fabricate sub-nanometer MOS transistor, is being demonstrated through an ion implantation step by the TSUPREM4 process simulator and MEDICI device simulator. The main objective of this report is to investigate the effects of the vacancies on device performance. Crystalline (100) silicon wafers of n-type with concentration of 10^16 cm^-3 uniformly distributed are used throughout the simulation. High concentrations of vacancies are introduced into the silicon substrate by BF2 implantation. The positions where the vacancies are being located within the silicon substrate can be controlled by modulating the implant energies. With the vacancies incorporated into the silicon substrate, it reduces the junction depth (Xj) after the post activation annealing. It is significant to mention that the fabrication steps involved in the simulations slightly differs from the main fabrication process steps in the industry.
URI: http://hdl.handle.net/10356/17983
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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