Model boosting for error checking in recovered layouts from microscopic IC images

Abstract

In the rapidly advancing field of integrated circuit (IC) technology, microscopic IC image analysis has become essential for addressing hardware security challenges such as Trojan horse detection, intellectual property infringement detection, and integrity checking. By extracting design-level information from physical ICs, detailed functional analysis can be performed. However, recovering IC layouts using advanced deep learning techniques poses significant challenges, particularly with circuit-level errors like opens and shorts. This project aims to augment multiple deep learning models to automatically check for errors in recovered layouts, thereby enhancing the accuracy and reliability of functional analysis. Notably, the Stacking_by_miniU-Net model achieves a Mean Intersection over Union (Mean IoU) of 0.9342 and a Mean Accuracy of 96.86%, outperforming other models. Furthermore, the Stacking model shows effective identification and mitigation of circuit errors, especially in challenging segmentation cases.