Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/18079
Title: CMOS PLA design
Authors: Dilparinder Singh
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2009
Abstract: Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits are the enabling technology for the modern information age. Digital CMOS integrated circuits have been the driving force behind Very Large Scale Integration for high-performance computing and other scientific and engineering applications. The demand for digital CMOS ICs will be continually strong due to salient features such as low-power, reliable performance, circuit techniques for high speed such as using dynamic circuits and ongoing improvements in the processing technology. Programmable logic arrays (PLAs) which are used to realize the control logic circuits in CPU and DSP VLSI circuits form a very important building block of the CMOS VLSI systems. Several new configurations for the design of PLAs have been proposed in the literature recently. In this project, in-depth understanding of the digital integrated circuits and CMOS topics was attained and Virtuoso Schematic Capture and Spectre Simulation techniques were learnt through Cadence software. Simulations were carried out for different classes of CMOS Digital Integrated Circuits and also performance comparisons were done on various proposed PLA designs through Cadence simulations in terms of Speed and Power.
URI: http://hdl.handle.net/10356/18079
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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