Machine learning for high-dimensional data analysis in hardware assurance applications

Abstract

Hardware Assurance (HA) of Integrated Circuit (IC) is of paramount importance for the security and integrity of ICs after manufacturing. This is usually done by first extracting the circuit connections in the form circuit netlist and subsequently analysing the circuit netlist. The analysis of circuit netlist involves high-dimensional graph data with rich features. Manual analysis proves impractical. Conventional approaches are inefficient for feature analysis. To this end, this thesis explores using graph-based structural analysis for an automated circuit analysis. It converts circuits into equivalent circuit graph representations and subsequently develops graph-based analysis to interpret circuits based on their structural properties. It develops novel Graph Neural Network (GNN) based machine learning methods to perform circuit analysis tasks in HA, including circuit partitioning, circuit recognition, circuit obfuscation and circuit error correction. The outcome of this thesis work opens new opportunities of AI in HA.