Design of low-quiescent low dropout regulator with sustainable performance

Abstract

As System-on-Chip (SoC) applications in the Internet of Things (IoT) continue to grow, the demand for efficient power management has steadily increased. Low-Dropout Regulators (LDOs), as a vital element in power management systems, significantly influence SoC performance. A key area of current research on LDO regulators is the reduction of quiescent power consumption while maintaining good transient response. Moreover, with the rising level of SoC integration, capacitorless LDOs (OCL-LDO regulators) have become increasingly popular in SoC applications. This project presents a low-power Level Shift Flipped Voltage Follower (LSFVF) capacitorless LDO regulator, which is designed using the TSMC 40nm Process Design Kit (PDK). The design incorporates a dynamic cascode biasing circuit to enhance transient response. By replacing the single control transistor in the LSFVF with composite cascode transistors, the loop gain of the LSFVF is increased, leading to improved line and load regulation, as well as enhanced accuracy of the LDO regulator. Additionally, employing a 2-stage operational amplifier (opamp) instead of a 1-stage symmetrical operational transconductance amplifier (OTA) for the control circuit, it enhances the reference voltage tracking capability, further improving regulation performance. The simulation results using Cadence tools demonstrated that, with an input voltage of 1.2V, the dropout voltage is 200mV, and the quiescent current under no-load conditions is 768.2nA. For a 50pF load capacitor, under a 0-10mA load current and a 1µs edge time, the value for the overshoot is obtained as 31.22 mV, while the undershoot reaches 75.48 mV, and the settling time to 1% accuracy is 595µs.