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|Title:||Simulation and verification of IP cores for PCI and ethernet application||Authors:||Xu, Ying.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems||Issue Date:||2009||Abstract:||PCI and Ethernet MAC are two most essential and widely-used modules in computer systems and networking. A project was carried to study two IP Cores, namely a PCI Bridge IP Core and an Ethernet MAC IP Core, aiming to understand the functionalities and specifications of the two cores, hence facilitating the reuse of these cores in ASICs (Application Specific Integrated Circuits). The report covers the study, simulation and verification of the two cores. The two IP cores are available as synthesizable RTL (Register Transfer Level) core coded in Verilog HDL (Hardware Description Language). The codes and functionalities of the two cores were first studied and analyzed. Their functionalities were compared with the PCI and the Ethernet MAC standard specification. To verify their functionalities, a set of testbenches was developed in Verilog HDL, targeting the main functions of the cores, namely data transactions, configuration and interrupt reaction. An integrated system consisting of the two cores was then created to form a complete communication link and a system level testbench was developed to verify the integrated system. The report presents the details of the functionality and specification description of the two cores, the testbenches developed, the simulation process and the results obtained as well as the result analysis. Some problems encountered and the solutions found are discussed. Some suggestions for future work are also included in the report.||URI:||http://hdl.handle.net/10356/18187||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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