Design and comparison of adder topologies for high performance computing

Abstract

Efficient adder design is critical for enhancing high-performance computing systems. This dissertation explores the design, implementation, and analysis of radix-2 adders, with a particular focus on parallel prefix adder topologies. The study begins with a comprehensive review of existing adder architectures, including simple adders, carry-select adders, and various parallel prefix designs such as Kogge-Stone, Brent-Kung, and Ladner-Fischer. Through theoretical analysis and practical implementation using Verilog and EDA tools, the research evaluates the timing, power consumption, and area utilization of these adders, providing a comparative analysis of their strengths and weaknesses. Results highlight the trade-offs between speed, power efficiency, and area, offering insights into optimal adder selection for specific applications. Limitations of the study and potential areas for future work, such as exploring emerging technologies and optimizing adder designs for specialized applications, are discussed. This research contributes to advancing efficient arithmetic designs in modern computing