Automotive SoC scan and automatic test pattern generation

Abstract

Cell-Aware Test (CAT) is an advanced testing methodology designed to address the growing limitations of traditional fault models like Stuck-At and At-Speed testing. With the continued scaling of semiconductor technology, manufacturing defects increasingly occur within the internal structures of standard cells, which are often overlooked by conventional testing approaches. CAT overcomes this limitation by focusing on detecting faults inside standard cells rather than just at their input and output boundaries. This thesis provides a detailed evaluation of CAT's strengths and limitations as compared with normal boundaries fault detection. The study reveals that CAT significantly improves defect coverage, particularly in Stuck-At mode, where it achieves up to three times the fault detection compared to traditional methods with only a modest increase in pattern count. However, the effectiveness of CAT in Transition mode is less pronounced, as the fault list expands only marginally, while the required patterns increase significantly leading a longer simulation running time, which limiting its practical benefits. These findings highlight the need for further research to optimize CAT. One of the main challenges in deploying CAT is the dependence on User-Defined Fault Models (UDFMs), which require extensive effort and resources to develop. Additionally, the larger fault lists in CAT increase ATPG runtime, making it less suitable for time-critical testing scenarios. Despite these challenges, CAT demonstrates clear advantages in detecting complex, hard-to-detect faults, contributing to improved product reliability and lower Defective Parts Per Million (DPPM).