CMOS digital multiplier IC design for mobile applications

Abstract

The multiplier is one type of logic algorithm unit which is very commonly implemented in digital integrated circuits such as Central Processing Unit (CPU) and Graphic Processing Unit (GPU). Due to demands of the industry, high-speed multiplier circuits design is quite common. However, with the development of the process and integration, the power dissipation of multipliers become a critical problem. This research concentrates on the design of low power multiplier for mobile applications. The ultimate goal is to design 16-bit signed and unsigned low power multipliers with relatively high speed. The research based on Radix-4 Booth algorithm, Wallace tree and Dadda tree compression techniques, explores the performance, power and area of circuits under different optimization methods. The circuit design is implemented by Verilog hardware description language and the Synopsys VCS tool is applied to complete the function verification. Later, the synthesis flow based on STM65nm process is executed by Design Complier to obtain the netlist and performance data. The power dissipation of this design is 0.2434mW and the critical path delay is 1.85ns.