IC design of phase-locked loop in three-layer multi-gas sensing system

Abstract

With the advancement of communication technology and semiconductor processes, some key modules in on-chip systems that require clock signals as drivers, such as analog-to-digital converters and serial interfaces, are operating at higher frequencies, which puts higher demands on the quality of clock signals. This article focuses on the application of phase-locked loops in on-chip clock generation circuits, which requires phase-locked loops to have low phase noise and low jitter. The dissertation first analyzes the working process of the phase-locked loop and models and analyzes it to understand the loop characteristics of the phase-locked loop. Then, it discusses the specific implementation of each module circuit and the analysis and solutions of non-ideal factors. Afterwards, the established model was used to analyze the impact of loop bandwidth on the phase noise of the phase-locked loop, and to select an appropriate bandwidth through graphical methods to ensure lower jitter performance. In addition to selecting the appropriate loop bandwidth, adopting more advanced phase-locked loop architectures at the system level can achieve better phase noise performance. For example, ultra wideband phase-locked loops can greatly increase the bandwidth to suppress the phase noise contributed by VCO, undersampling phase-locked loops can greatly suppress the in band noise introduced by charge pumps, and injection locking can reduce the phase noise of VCO. Under the 18nm CMOS process, the final simulation results show that the output frequency range of the phase-locked loop is 2 ∼ 2.7GHz. When the output frequency of the phase-locked loop is 2.7GHz, the lock time is 8µs, and the power consumption is 27.3mW. The calculated phase noise at the 1MHz frequency offset of the phase-locked loop is 93dBc/Hz.