Low power digital IIR filter bank IC design

Abstract

This dissertation presents the design of a 16-bit low-power 10th-order IIR filter optimized for power efficiency in cascade form. The filter design leverages advanced multiplier techniques, including the implementation of the Dadda multiplier and a pre-encoded Booth Radix-4 multiplier. A comprehensive overview of IIR (Infinite Impulse Response) filters is provided, focusing on the characteristics of different forms, including direct, cascade, and parallel forms. The power consumption of integrated circuits is also discussed, with an emphasis on the components and factors influencing power dissipation, as well as widely used low-power techniques. The filter’s design process includes MATLAB modeling, coefficient quantization, SOS (Second Order Section) decomposition, and the structural design of the 10th-order IIR filter. The dissertation also evaluates the performance and power consumption of the implemented multiplier architectures and validates the design through extensive analysis. The proposed low-power design achieves a 68.34% reduction in power consumption, making it a promising solution for power efficient digital signal processing applications like wearable health monitors and IoT (Internet of Things) devices.