High fidelity control of superconducting and Si qubit

Abstract

This Master thesis first reviews the current state of different kinds of qubit, providing a comprehensive analysis of the development progress and future directions of qubit control and readout schemes, which are key components of quantum computers. Special emphasis is placed on analyzing and designing the cryo-CMOS qubit state controller (QSC) chips for transmon qubits, followed by an analysis of the performance of the current state-of-the-art chips, summarizing the development directions and challenges faced. Subsequently, the progress and achievements of previous work, based on 28-nm CMOS, are presented. This work utilizes submodules that are more power-efficient and better suited to cryogenic temperature (CT). Based on our modeling work, we simulate the chip at both room temperature (RT) and 4 K. The results, showing an SFDR of 45 dB, an SNR of 58 dB, and a power consumption of 6 mW per channel under active control at 4 K, with minimal performance degradation compared to RT, suggest that this work is a strong candidate compared to the previous state of the art.