RISC-V + MRAM: integrating off-chip rapid non volatile memory with a RISC-V core on FPGA

Abstract

The proliferation of Artificial Intelligence (AI) and Machine Learning (ML) over the previous years has been possible due to the increased ability to train larger Deep Neural Networks (DNNs) with increasing amounts of data. With the rise of more sophisticated and complex models, lower-end computational devices (running smaller machine learning models such as TinyML) do not have the capacity to store the necessary model weights, data structures, etc. This has resulted in researchers looking into using off-chip memory to overcome hardware limitations, with the caveat of limited memory access speeds and energy efficiency. In order to optimize the use of off-chip memory, this project will focus on integrating Magnetoresistive RAM (MRAM) with NTU’s self-developed RISC-V microprocessor, the ECS-DOT SoC. MRAM is a non-volatile memory with read/write speeds comparable to SRAM/DRAM, and writes to memory are nondestructable. These traits make MRAM a highly attractive off-chip memory option. As such, this project aims to create a prototype Integrated Chip (IC) using an FPGA to integrate an off-chip MRAM with the ECS-DOT SoC. The synthesized FPGA design needs to balance between having fast memory access times and using the least amount of Input/Output (I/O) pins. Designing this interface is an iterative process: starting from Serial-Parallel-Serial (SPS) modules, SPS with burst functionality, and finally integrating with standard serial protocols such as SPI. Additionally, we will also be testing the read/write speeds of each of the designs using a logic analyzer, determining the efficacy of both the designs and MRAM as a viable off-chip memory option.