Interactions between cache coherence and network-on-chip

Abstract

This thesis aims to investigate how Cache Coherence Protocols (CCPs) and Network-on-Chip architectures interact in maycore systems using full-system simulations. We integrate and compare five coherence protocols, namely MESI Two Level, MESI Three Level, MOESI CMP directory, MESIF (customized via SLICC) and the ARM Coherent Hub Interface (CHI). These protocols are evaluated across six distinct NoC topologies (ring, 2D mesh, torus, crossbar, point-to-point, and a custom 2D mesh variant) under realistic multithreaded workloads from the PARSEC benchmark suite.

Key contributions of this work include: a custom SLICC-based implementation of the MESIF protocol that optimizes shared-read efficiency via a forward state; the development of an automated benchmarking framework using gem5art combined with Bayesian optimization to efficiently explore the large configuration space; and the enhancement of NoC Quality-of-Service (QoS) functionality to prioritize latency-sensitive coherence transactions. Despite the extensive integration challenges encountered, including long build and simulation times, and manual Linux kernel configurations, limited the collection of complete quantitative results within the project timeline, the design and methodology presented lay a foundation for future research.

The findings and insights from this project look to underscore the need for balance between coherence protocol design and NoC performance and provide a framework for scalable, energy-efficient manycore architectures.