FPGA implementation of hardware accelerator for LSTM networks

Abstract

This thesis presents an FPGA-based accelerator for Long Short-Term Memory (LSTM) inference, specifically designed for energy- and areaconstrained edge applications. The accelerator integrates a deeply pipelined 8×8 systolic array for efficient matrix multiplication with specialized fixedpoint arithmetic (Q4.28 input, 8-bit outputs) and employs LUT-based approximations for the tanh and sigmoid activation functions. The design is implemented with standardized AXI and APB interfaces for integration into heterogeneous SoC platforms and is synthesized and integrated at a 100 MHz constraint. Synthesis and post-place-and-route results demonstrate low resource utilization (¡5% overall logic, ¡30% DSP usage for the systolic array) and low dynamic power consumption, validating the design’s suitability for real-time, low power edge inference.