16-bit high performance low power CMOS multiplier IC design

Abstract

The growing computational demands of edge AI applications necessitate multiplier architectures that simultaneously achieve high performance and low power consumption. This paper presents a special Booth-Wallace multiplier design that successfully fulfills these dual objectives through innovative circuit-level optimizations. Employing Radix-4 Booth encoding and Wallace tree compression techniques, the proposed architecture incorporates several key low-power design strategies including module data reuse, optimized sign-bit encoding, and an improved 4:2 compressor structures. The design has a pipeline that maintains high-performance operation while effectively minimizing dynamic power dissipation. Implemented in Verilog HDL and verified through VCS+DC synthesis, this high-performance low-power multiplier demonstrates significant improvements over traditional design. The optimized architecture achieves a 112.8% frequency increase from 235MHz to 500MHz while simultaneously reducing power consumption by 10.2% to 1.7913mW. This performance enhancement is attained with a controlled 31% area increase, representing an optimal balance for power-constrained edge computing applications. Experimental results confirm that the proposed techniques effectively address the fundamental challenges of maintaining high-speed operation while reducing power consumption in modern multiplier designs.