Low power circuit techniques for SRAM-based computing-in-memory macros

Abstract

With the growing demand for higher energy efficiency and computing throughput in artificial intelligence and big data applications, Compute-In-Memory (CIM) has emerged as a promising architecture to overcome the limitations of the traditional von Neumann model. This thesis focuses on SRAM-based CIM designs, providing a comprehensive analysis of both conventional 6T SRAM and advanced 8T SRAM cells in terms of structure, performance, and applicability to CIM operations. The study begins with a review of SRAM architecture evolution and evaluates key performance metrics—power consumption and stability—under CIM constraints. Read/write and MAC operations of 6T and 8T SRAM cells are modeled and simulated to explore their behavior during in-memory computation. 6T SRAM cell suffers from reduced noise margins (RSNM = 104.51 mV, WSNM = 389.29 mV), making it vulnerable to read/write disturbances. In contrast, the 8T SRAM cell provides higher read stability (RSNM = 273.15 mV) and supports more robust MAC operations, though with moderately higher power consumption. Subsequently, 64-bit memory arrays based on both SRAM types are constructed and analyzed to assess large-scale integration effects on reliability and overhead. Simulation results show that while 6T SRAM is area- and energy-efficient, it suffers from reduced stability under aggressive scaling and CIM-specific workloads. In contrast, the 8T SRAM cell, with its decoupled read/write paths, exhibits improved robustness and better suitability for parallel in-memory operations, making it a stronger candidate for edge AI and data-intensive applications.