Analog computing-in-memory using SRAM

Abstract

This dissertation investigates the potential of Static Random-Access Memory (SRAM)-based Computing-In-Memory (CIM) to address the von Neumann bottleneck in energy-intensive machine learning applications. By integrating computation directly within memory arrays, the proposed architecture minimizes data movement overhead while enabling high-throughput multiply-and-accumulate (MAC) operations critical for convolutional neural networks (CNNs). A functional 8×8 SRAM array, implemented in TSMC 65nm technology, demonstrates robust read/write operations and resolves the write-disturb issue through a transition from 6T to 8T bit cells. This structural enhancement stabilizes MAC operations by isolating computational pathways from stored data. Further optimization of peripheral circuits, including a configurable Word-Line Digital-to-Analog Converter (WLDAC), improves signal margin (113.99 mV) and reduces integral nonlinearity (INL) to 0.06 LSB by tuning sampling and discharge times. The dissertation validates a 64-bit SRAM array capable of parallel 8-row MAC operations, achieving energy-efficient in-memory computation. These advancements highlight SRAM-CIM’s scalability for edge AI and AIoT applications, offering a pathway to overcome the memory wall while maintaining compatibility with advanced logic technologies.