Low power PLL design based on 55nm BCD-lite

Abstract

In wireless communication systems, PLL frequency synthesizers are widely used in wireless transceivers because of their high output stability, low power consumption and easy integration, which provide stable clock signals for data transmission and reception. The rapid development of wireless communication technology has put forward higher requirements for the integration and power consumption of PLL frequency synthesizer. This paper mainly studies the PLL circuit, and analyzes the research status, principle and architecture. On this basis, a low-power charge pump integer PLL circuit is designed, which mainly includes frequency discriminator, charge pump, low-pass filter, voltage-controlled oscillator and frequency divider and other sub-modules. A low-power charge pump PLL circuit is designed with input frequency of 40MHz, division ratio of 63, output frequency of 2.52GHz and phase noise of -88dBc/Hz@1MHz, power consumption is 1.89mW, locking time is about 3μs.