High-performance low-dropout regulator design for SoC applications in nanoscale CMOS

Abstract

This dissertation presents the design and implementation of a high-performance low-dropout (LDO) voltage regulator with an integrated bandgap reference (BGR) in 65 nm CMOS technology. The proposed LDO targets high power supply rejection ratio (PSRR), fast transient response, and low quiescent current, making it suitable for low-power System-on-Chip (SoC) and Internet of Things (IoT) applications. A segmented pass transistor structure is employed to support a wide range of load currents while minimizing dropout voltage. An error amplifier with adaptive biasing and a source-follower buffer is used to improve PSRR and transient behavior. The BGR circuit is based on a BJT architecture with curvature compensation, achieving a temperature coefficient as low as 8.178 ppm/°C. Extensive simulations—including DC, AC, transient, noise, PSRR, and loop gain analysis—are conducted across various process corners and temperatures. Post-layout results confirm PSRR above 80 dB, settling time under 100 ns, and quiescent current below 50 µA. The design achieves excellent regulation performance, demonstrating strong integration potential for modern low-power mixed-signal systems.