Tiny machine learning accelerator design in VHDL

Abstract

This paper presents a design of neural network accelerator based on Verilog. This structure can improve the throughput of convolutional neural network. By adopting pipeline structure to improve the utilization of DSP, in addition, the convolution operation is further optimized, such as sparse processing to reduce unnecessary operations before convolution, and Winograd algorithm to lower the utilization of multiplier. In this accelerator, the multiplication operation can be decreased by more than 80%.