In-memory computing

Abstract

In-memory computing refers to the cutting-edge technology of data storage and processing within computers. All computers today adopt the von Neumann architecture. This structure consists of the Central Processing Unit (CPU), Memory Unit and Input/Output. The memory storage system used in this architecture is known as random access memory (RAM). RAM is a short-term memory storage within a software that allows the processor to run optimally. In recent years, RAM has become a fundamental part of our everyday lives. It propels every sector’s basic task performance on computers smoothly and efficiently. However, with up-and-coming developments like the Internet of Things (IoT) and big data, large amounts of information are required to be processed and retrieved at real time that cannot be managed by RAM. The data deluge in RAM then poses an imminent challenge – the memory bottleneck. The memory bottleneck is resulted by the communication latency between the processor and memory units in the traditional von Neumann architecture. As such, an alternative strategy of integrating the memory and processor units within one chip has been implemented. This can be seen in many new types of RAM designs, of which include the Static Random Access Memory (SRAM), Resistive Random Access Memory (RRAM) and more. This report examines the feasibility of SRAM in the new age of in-memory computing, the plausible SRAM cell designs, and future works to be done for better performance of computer memory. The results and findings within this report are generated with the use of Cadence Virtuoso with components within the TSMC65nm technology library.