Low power secure IC design

Abstract

Mathematically secure encryption algorithm such as Advanced Encryption Standard (AES) play a crucial role in a lot of security systems, such as banking and military applications. The encryption algorithm protects the sensitive data from being accessible by the adversaries as the encrypted data are not readable without the secret key. However, as the encryption algorithm is physically implemented as a hardware, the stored key is potentially leaked out with a cyber-physical attack. The cyber-physical attack can reveal the secret key by analyzing the power dissipation and electromagnetic (EM) emanation of the hardware during the encryption process, known as Side-Channel Attack (SCA). In this project, the hardware accelerator for an AES algorithm will be designed and implemented on a Field Programmable Gate Array (FPGA) and on ASIC. SCA will be performed to evaluate the security level of the hardware design. At the end, student can analyze and understand the leakage trend of the hardware implementation of encryption algorithm.