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https://hdl.handle.net/10356/184778
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DC Field | Value | Language |
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dc.contributor.author | Chang, Po Yan | en_US |
dc.date.accessioned | 2025-05-08T04:35:38Z | - |
dc.date.available | 2025-05-08T04:35:38Z | - |
dc.date.issued | 2025 | - |
dc.identifier.citation | Chang, P. Y. (2025). Security risk evaluation for logic locking. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/184778 | en_US |
dc.identifier.uri | https://hdl.handle.net/10356/184778 | - |
dc.description.abstract | Globalisation of the Integrated Circuit (IC) supply chain has resulted in significant security challenges, as untrusted entities such as third-party manufacturers pose a threat to intellectual properties leading to economic losses. Unauthorised modifications, hardware trojans, and IC piracy have incurred substantial economic losses for chip designers and semiconductor companies. Logic locking has emerged as a significant countermeasure for securing IC designs by adding security features making it difficult for attackers to reverse-engineer or tamper with the circuit. However, as attack methodologies evolve, existing logic locking schemes are being compromised by advanced techniques like oracle-less attacks. Naïve MUX-based logic locking, initially introduced as a defence, was found vulnerable to oracle-less attacks such as SWEEP and SAAM. To address this weakness, D-MUX logic locking was developed, which incorporates specific schemes ensuring each path through the MUX has the same probability of being true or false. While D-MUX proved effective against prior attacks, it was later broken by MuxLink, a machine learning based attack. This report introduced SimLL, a novel structural similarity-based logic locking technique to counter the efficiency of MuxLink. Through link and node clustering, SimLL inserts key gates in structurally similar positions, disrupting MuxLink’s ability to predict keys accurately. Experimental results on the ISCAS-85 and ITC’99 benchmark circuits demonstrate that SimLL reduces MuxLink’s accuracy (AC), prediction (PC), and key prediction accuracy (KPA) compared to D-MUX. SimLL reduces the metrics with an average AC, PC, and KPA of 43.03%, 79.94%, and 65.17% on ISCAS-85 and 59.52%, 89.40%, and 84.05% on ITC’99, representing the reduction in the effectiveness of the MuxLink attack as compared to D-MUX, where metrics exceed 95% on both benchmarks. While SimLL enhances security, it introduces additional computational overhead due to its clustering-based approach. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Nanyang Technological University | en_US |
dc.subject | Engineering | en_US |
dc.title | Security risk evaluation for logic locking | en_US |
dc.type | Final Year Project (FYP) | en_US |
dc.contributor.supervisor | Gwee Bah Hwee | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Bachelor's degree | en_US |
dc.contributor.supervisoremail | ebhgwee@ntu.edu.sg | en_US |
dc.subject.keywords | Logic locking | en_US |
item.grantfulltext | restricted | - |
item.fulltext | With Fulltext | - |
Appears in Collections: | EEE Student Reports (FYP/IA/PA/PI) |
Files in This Item:
File | Description | Size | Format | |
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FYP_Final_Report_ChangPoYan.pdf Restricted Access | 3.8 MB | Adobe PDF | View/Open |
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