Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/18685
Title: Accelerating the interior point method on a FPGA
Authors: Koh, Christopher Seng Lee
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2009
Source: Koh, C. S. L. (2009). Accelerating the interior point method on a FPGA. Master’s thesis, Nanyang Technological University, Singapore.
Abstract: With the dawn of reconfigurable computing, the FPGA has increasingly replaced microcontrollers as a viable alternative in the arena of embedded applications especially in DSP or high performance control applications. FPGA provides engineers the flexibility to employ significant architectural speed-up using techniques such as pipelining and parallel processing, normally not possible in off-the-shelf processors. Such customized hardware solutions however, hold the primary drawback of long development cycles. The emergence of re-configurable soft-core processors on FPGA during the past decade has changed this reality. Embedded engineers now have an additional option to build a firmware solution running on a reconfigurable microprocessor on FPGA. In addition, they also enjoy the added flexibility of using the remaining resources on the FPGA to build customized hardware-based Co-Processor or accelerators to further enhance the performance the microprocessor. A tightly coupled Co-Processor in co-existence with carefully coded firmware running on a microprocessor could effect in an improvement in performance, whilst maintaining a relatively shorter development life cycle.
URI: https://hdl.handle.net/10356/18685
DOI: 10.32657/10356/18685
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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