Comparison of some time slot allocation schemes in TDD-CDMA multihop cellular networks
Date of Issue2008
School of Electrical and Electronic Engineering
Network Technology Research Centre
Cellular networks are becoming more and more popular among people these days and at the same time digital multimedia technologies and Internet services are advancing. These progresses result in new demands in mobile communications that can support different services as well as high data rates. Thus, new technologies are deployed in cellular systems in order to increase their capacity and performance. One of the proposed solutions is to combine the idea of ad hoc networks and cellular networks to design a cellular system that can support multi-hop transmission. These systems are called Multi-hop Cellular Networks (MCN). This technique improves capacity and coverage of conventional single-hop cellular systems.This Thesis focuses on implementing MCNs based on Code Division Multiple Access (CDMA) networks with Time Division Duplexing (TDD). Performance of various time slot allocation schemes in TDD-CDMA systems are studied and compared in single-hop and multi-hop scenarios. Our goal is to find the best-performing time slot allocation scheme in such systems. First, we study performance of time slot allocation schemes in TDD-CDMA cellular systems and investigate the effect of employing multi-hop data relaying in such systems. Maximum capacity of these schemes will be compared. A multi-hop time slot allocation scheme, Maximum Interference First, is proposed in this study. This scheme reduces crossed-time slot interference and utilizes allocation of time slots by assigning new user to time slots that receive high interference and support the user with maximum data rate. Thus, low-interfered time slots will be reserved for coming users with weak signal qualities. Simulation results show that this scheme outperforms others in terms of overall capacity in all traffic scenarios.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits