dc.contributor.authorSee, Guan Huei
dc.date.accessioned2009-07-07T03:54:59Z
dc.date.accessioned2017-07-23T08:32:29Z
dc.date.available2009-07-07T03:54:59Z
dc.date.available2017-07-23T08:32:29Z
dc.date.copyright2009en_US
dc.date.issued2009
dc.identifier.citationSee, G. H. (2009). Scalable compact modeling for nanometer CMOS technology. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/18733
dc.description.abstractThis thesis documents the compact model developed for bulk MOSFET and double-gate MOSFET. The unified regional modeling approach is used in the physics-based scalable model development for bulk and double-gate MOSFETs. Surface potential models are developed regionally in accumulation, weak accumulation, depletion, volume and strong inversion regions, which are subsequently combined using interpolation functions to ensure smooth higher order derivatives. New unified regional-based short-channel effects are developed to improve the physical scalability of the charge model. A new concept that defines two separate saturation voltages at source and drain, referenced to bulk (or ground for double-gate), respectively, is introduced to meet the Gummel symmetry requirement and to allow possible extension to asymmetric source/drain devices within the same core model. A novel approach to unifying compact models for different non-classical MOS structures, such as ultra-thin body SOI and symmetric/asymmetric double-gate MOSFETs, is proposed. Explicit surface and zero-field potentials for common-gate asymmetric double-gate MOSFETs are solved regionally and the unified solutions are applied in the explicit drain-current model for double-gate MOSFETs. Explicit surface potentials for double-gate MOSFET with quantum mechanical correction are also developed. The research demonstrates a closer step towards the unification of MOS models for future generation non-classical MOS devices.en_US
dc.format.extent229 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Semiconductorsen_US
dc.titleScalable compact modeling for nanometer CMOS technologyen_US
dc.typeThesis
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorZhou Xingen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en_US


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