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Title: High speed prescaler for bluetooth application
Authors: Chu, Dennis Wah Tat.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2008
Abstract: Capitalizing on the human insatiable need for information, many consumer products has incorporated wireless standards such as IEEE 80211, Bluetooth and Zigbee to allow for rapid information exchange even on the go. The original intent of allowing the user to be connected everywhere he/she goes implies that the product has to be portable. The portability translates into limited real estate for the energy source and circuitry. To combat this, many development groups sought to realize a fully integrated transceiver capable of low power operation. The focal point when tackling the transceiver’s power consumption is the frequency synthesizer which is usually formed by a Phase-Locked Loop (PLL) since it accounts for a majority of the total power consumed. The performance in power consumption and channel selection of the frequency synthesizer are limited by the frequency divider and voltage-controlled oscillator (VCO). The objective of this work is to design a Divide-by-15/16 Prescaler which can be then integrated in an N- Divider for Bluetooth application. The Prescaler will be realized using Chartered Semiconductor Manufacturing Limited CMOS technology (0.18-μm CMOS process). The power consumption reduction and speed enhancement are realized through the use of asynchronous and synchronous logic for the overall division and usage of dynamic circuit technique in designing the D Flip-Flop using in the division. The dynamic CMOS divide-by- 15/16 Prescaler is implemented in this project. The design is based upon the True Single Phase Clock (TSPC) and Extended True Single Phase Clock (E-TSPC) techniques. The power consumption achieved is 3.3 mW, at a supply voltage of 1.8 V.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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