Modelling and various suppression techniques of cross-coupling in high-speed digital design

Abstract

In today’s demand for faster data rates and more features to be integrated on single printed circuit board (PCB), the performance and reliability of the system becomes increasingly affected by the performance of the printed circuit interconnects. As the timing budget becomes tighter due to higher data rates, the issue of signal integrity (SI) can no longer be ignore. Furthermore, a wider bandwidth is resulted as the clock speed of the system increases. One of the major issues in SI is the effect of trace-to-trace coupling, or commonly known as crosstalk. As the routing of the PCB get denser and the operating clock frequency of the system increases, crosstalk must be taken into consideration in the layout of the digital board to avoid possible critical system failure. In this project, various design methodologies in increasing the crosstalk immunity deployed in high speed PCB designs will be investigated. With a very comprehensive study of these design methodologies, the design guidelines for different levels of crosstalk immunity are established so that designers could choose the right design method for any specific crosstalk requirements.