Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/18829
Title: Universal asynchronous receiver/transmitter (UART) design for acoustic signal processor (ASP) based on globally asynchronous locally synchronous (GALS) logic
Authors: Lim, Melvin Yuan Jie.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2008
Abstract: Synchronous design methodology offers access to a wide range of sophisticated development tools and mature designing techniques. Conversely, asynchronous design methodology presents a graceful solution to undesirable clock issues and high power dissipation. Merging the advantages of both design methodologies, a hybrid synchronous/asynchronous approach using Globally-Asynchronous-Locally-Asynchronous (GALS) is employed in the implementation of a low power Acoustic Signal Processor (ASP). Being a replica of an existing synchronous ASP, the proposed GALS-ASP has the exact Digital Signal Processing (DSP) algorithms with some additional operations and features. In that, a Universal Asynchronous Receiver-Transmitter (UART) module is implemented for the purpose of interfacing with the external world through serial communications. For the need of having an accurate benchmarking of power dissipation, the existing synchronous ASP is analysed and re-prototyped for power analyses. Both will be compared to determine and quantify its improved power attributes. With this new architecture, the propose GALS-ASP is implemented in both Field-Programmable Gate Array (FPGA) technology (using the same Altera EP2C8T144C8) and Application-Specific Integrated Circuits (ASIS) technology (using IBM 0.13 μm CMOS process). Both technologies are adopted to demonstrate different aspects of GALS-ASP. On the other hand, the ASIC technology goes on to show its low power feature. This project only focuses on the implementation of the proposed GALS-ASP using FPGA technology. ASIC implementation is not within the scope of this project as it has been undertaken in another project.
URI: http://hdl.handle.net/10356/18829
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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