Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/19266
Title: Wire level encapsulation framework for increasing FPGA design productivity
Authors: Oliver, Timothy Francis
Keywords: DRNTU::Engineering::Computer science and engineering::Hardware::Logic design
Issue Date: 2009
Source: Oliver, T. F. (2009). Wire level encapsulation framework for increasing FPGA design productivity. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: This thesis explores the performance impact of optimising the components of a Field Programmable Gate Array (FPGA) system down to the lowest level independently from other parts of the system. The motivation for this is that not only is the design and verification effort put in to a component reused, the optimisation effort expended in mapping, placement and routing is also reused. FPGA technology has its roots in digital circuit design and, like every silicon technology, it advances every 18 months, doubling the gate capacity available to the designer. The single largest threat to this growth is the gap that is forming between the number of available gates and the ability of designers to use these gates in the time frame of a typical design cycle. The design gap is more acutely felt in the FPGA computing community since the main perceived strength of FPGA technology is its reconfigurability. As an example, High Performance Computing (HPC) on FPGA offers a clear advantage. However, designer productivity issues are a major threat to its wide spread use. HPC is achieved on FPGA by specialising the architecture. Specialisation implies a design process. Thus, designer productivity is the main restricting factor to increasing the computing functionality that FPGA systems can offer.
URI: https://hdl.handle.net/10356/19266
DOI: 10.32657/10356/19266
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Theses

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