dc.contributor.authorSantanu Kumar Dash
dc.date.accessioned2009-11-16T08:30:40Z
dc.date.accessioned2017-07-23T08:28:49Z
dc.date.available2009-11-16T08:30:40Z
dc.date.available2017-07-23T08:28:49Z
dc.date.copyright2009en_US
dc.date.issued2009
dc.identifier.citationSantanu, K. D. (2009).Profile driven schemes for energy-sensitive cache hierarchy. Master’s thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/19286
dc.description.abstractWith the advent of mobile and handheld devices, power consumption in embedded systems has become a key design issue. Of the components that consume significant amounts of power in an embedded system, cache memories have been reported to consume in excess of 40% of the total power in typical high end embedded processors. Therefore, cache memories are an obvious target of many low-power optimizations. Recently, it has been shown that cache requirements of the applications vary widely and a significant amount of energy spent in cache accesses can be saved by tuning the cache parameters according to the needs of the application. However, tuning the cache memory to suit the needs of the application entails identification of optimal cache configurations in the first place. With the large set of configurations to choose from, this process is prohibitively time consuming if done through exhaustive cache hierarchy simulations. Therefore, there exists a need for tools that can rapidly identify optimal cache configurations to tune the cache parameters for any given application.en_US
dc.format.extent146 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Hardware::Memory structuresen_US
dc.titleProfile driven schemes for energy-sensitive cache hierarchyen_US
dc.typeThesis
dc.contributor.researchCentre for High Performance Embedded Systemsen_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.contributor.supervisorThambipillai Srikanthanen_US
dc.description.degreeMASTER OF ENGINEERING (SCE)en_US


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