Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/19623
Title: Design and implementation of a high speed chess move generator
Authors: Jaya Shankar Pathmasuntharam
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Issue Date: 1996
Abstract: This thesis describes the design and implementation of high speed hardware chess modules which can be used to form a complete high speed chess machine. It describes how the large task of computer chess was parallelized and implemented on a field programmable gate array (FPGA) platform. The main modules which were time consuming and frequently used for control and decision of moves were translated into hardware. The main module comprises the move generator and the evaluator. The final design is a highly asynchronous one which will benefit from future advancement in circuit technology. Both the hardware evaluator and the hardware move generator designs are serial rather than time multiplexed. They are interfaced to a host PC which acts as the controller. The initial design is capable of handling 32 bits internal processing. However due to limitation of the medium-sized FPGAs, only a 16-bit design is implemented. Test results show that the hardware move generator has a raw speed of 2.78 million moves/sec. This is a 39% increase in speed compared to the design by Deep Thought[l] team. The hardware uses a total of 14 Xilinx FPGAs, 10 XC4013 and 4 XC4008 ICs.
URI: http://hdl.handle.net/10356/19623
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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