Performance analysis of ATM switches with bursty arrivals and finite capacity

Abstract

This Thesis looks into performance criteria such as cell loss probability, cell delay and delay jitter of different designs of ATM switches. The arrival process of ATM cells to each inlet of a switch is bursty as the traffic in the future B-ISDN can be expected to consist of compressed video and voice as well as data. Interrupted Bernoulli Process (IBP)is adopted in this Thesis to represent the input traffic. A simulation program has been developed for estimating the performance of ATM switches. Simulation for Knockout switch architecture is presented. The interrelation of the performance criteria (i.e. cell loss probability, cell delay and delay jitter), traffic characteristics, switch parameters (internal blocking and finite buffer size)and switch configuration under different operating conditions has been identified and analyzed.