Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits

Abstract

The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current gain of the bipolar transistor and the channel width and length, threshold voltage and the oxide thickness of the MOS transistor.