Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/19686
Title: Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
Authors: Sin, You Seng.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 1995
Abstract: The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current gain of the bipolar transistor and the channel width and length, threshold voltage and the oxide thickness of the MOS transistor.
URI: http://hdl.handle.net/10356/19686
Rights: NANYANG TECHNOLOGICAL UNIVERSITY
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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