Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/19803
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dc.contributor.authorChee, Piew Yoong.en_US
dc.date.accessioned2009-12-14T06:38:40Z-
dc.date.available2009-12-14T06:38:40Z-
dc.date.copyright1992en_US
dc.date.issued1992-
dc.identifier.urihttp://hdl.handle.net/10356/19803-
dc.description.abstractThis project attempts on integrating cross coupled circuit into two CMOS cells designed with new circuit techniques. Output buffer and current mode sense amplifier are the two circuits of interests. In addition, optimization of area utilization of SRAM cell column and its peripheral circuits is also investigated.en_US
dc.format.extent142 p.-
dc.language.isoen-
dc.rightsNANYANG TECHNOLOGICAL UNIVERSITYen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleCMOS cells design with cross-coupled latchesen_US
dc.typeThesisen_US
dc.contributor.supervisorLiu, Po-chingen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Engineeringen_US
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Appears in Collections:EEE Theses
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