Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/19807
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dc.contributor.authorGulam Mohamed.en_US
dc.date.accessioned2009-12-14T06:38:52Z-
dc.date.available2009-12-14T06:38:52Z-
dc.date.copyright1992en_US
dc.date.issued1992-
dc.identifier.urihttp://hdl.handle.net/10356/19807-
dc.description.abstractHigh level synthesis involves tasks that will transform an abstract or algorithmic level specification to a register transfer level structure while at the same time satisfying a set of constraints and achieving a set of goals. The system normally outputs a datapath structure which implements the specification together with a controller unit. The major tasks involved are : i) translation of input into graph-based representation; ii) operation scheduling; iii) allocation of resources; iv) creation of control unit based on the scheduled graph. Operation scheduling has been acknowledged to be one of the most important steps in high level logic synthesis. The quality of the final VLSI implementation is strongly dependent on the output of the operation scheduling system.en_US
dc.format.extent147 p.-
dc.language.isoen-
dc.rightsNANYANG TECHNOLOGICAL UNIVERSITYen_US
dc.subjectDRNTU::Engineeringen_US
dc.titleA heuristic-based scheduling algorithm for high level synthesis of digital systemsen_US
dc.typeThesisen_US
dc.contributor.supervisorTan, Han Ngeeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Engineeringen_US
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