A heuristic-based scheduling algorithm for high level synthesis of digital systems

Abstract

High level synthesis involves tasks that will transform an abstract or algorithmic level specification to a register transfer level structure while at the same time satisfying a set of constraints and achieving a set of goals. The system normally outputs a datapath structure which implements the specification together with a controller unit. The major tasks involved are : i) translation of input into graph-based representation; ii) operation scheduling; iii) allocation of resources; iv) creation of control unit based on the scheduled graph. Operation scheduling has been acknowledged to be one of the most important steps in high level logic synthesis. The quality of the final VLSI implementation is strongly dependent on the output of the operation scheduling system.