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|Title:||Computer-aided fault analysis of digital circuit||Authors:||Yip, Chee Soon.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||1992||Abstract:||Two test pattern generation programs are developed - bd and MoDalg. The bd implements the boolean difference method, an algebraic method that manipulates boolean equations to derive a complete test set for all possible stuck-at faults in the circuit under test.||URI:||http://hdl.handle.net/10356/19814||Rights:||NANYANG TECHNOLOGICAL UNIVERSITY||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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