FPGA implementation of low density parity-check (LDPC) coded recording channels

Abstract

Low Density Parity-Check (LDPC) codes have received lots of attention during the past decade due to their near Shannon-limit performance and decoding at very high rates. However, several issues have been raised in the research work with an aim to achieve the practical implementation of the LDPC codes. The first major issue is the performance evaluation of the LDPC codes and their decoding algorithms in the very low bit error rate (BER) regions. Unfortunately, there have so far been no analytical tools for the performance investigation of LDPC codes and one has to study such codes through simulations. The main problem with the simulations is their prohibitive execution time, especially for applications that require extremely low BERs such as data storage devices. Another concern is the efficiency of the decoding algorithm known as the Sum-Product algorithm. The Sum-Product algorithm is not optimized for short length codes and codes with cycles in their bipartite graph representation. On the other hand, the iterative decoding algorithm is computationally intensive, which imposes a high cost on area and power consumption of the decoder. The third issue is the design of the LDPC decoders to support different code lengths, rates and modes of operation.