Please use this identifier to cite or link to this item:
|Title:||Hot carrier reliability perspective on silicon-on-insulator lateral double-diffused MOSFET (LDMOS)||Authors:||Liao, Jie.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Semiconductors||Issue Date:||2010||Source:||Liao, J. (2010). Hot carrier reliability perspective on silicon-on-insulator lateral double-diffused MOSFET (LDMOS). Master’s thesis, Nanyang Technological University, Singapore.||Abstract:||Silicon-on-insulator (SOI) device has a buried silicon oxide (Buried Oxide, or BOX) layer extending across the entire wafer. Recently, there is an increased interest in SOI wafers for application to the fabrication of advanced CMOS ICs. SOI technologies offer a large number of advantages in terms of capacitances, less cross-talk and high integration density . One of the most common power MOSFETs used in smart power applications is SOI lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) because of its high speed, low on-state resistance, as well as the fabrication processes are compatible with the standard low voltage CMOS process . The performance of the SOI LDMOSFET is increased dramatically compared to the bulk technologies. However, SOI LDMOSFET is prone to hot carrier induced (HCI) degradation because the high operational voltages applied to the drain and/or gate will degrade the device electrical performance after prolonged operation. Many researches showed that the hot carrier reliability of a device is strongly dependent on its geometrical configuration, operational conditions, as well as the process parameters [3-5].||URI:||http://hdl.handle.net/10356/20920||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.